Remote Design Verification Engineer - System Verilog, UVM

Redmond, WA • San Francisco, CA Remote Available

Full-time $150k - $225k

Posted 05/06/2022

If you are a Design Verification Engineer with experience, please read on!

Based in the Bay Area, we are an innovative company that collaborates with Fortune 100 companies on innovative new technology. This includes autonomous driving and AR/VR applications.

What You Will Be Doing

- Hands on Verification environment development experience using Verilog and SV
- Development of verification plans
- Development of test cases and ensuring coverage and performance goals are achieved for IP and SOC level

What You Need for this Position

- 3+ years with Design Verification
- Experience with System Verilog
- Experience with UVM

What's In It for You

- Competitive Base Salary ($150k - $225k DOE)
- Vacation/PTO
- Medical
- Dental
- Vision
- 401k

So, if you are a SOC Design Verification Engineer with experience, please apply today!

Colorado employees will receive paid sick leave. For additional information about available benefits, please contact Dominik Sobaszek

This job is open to telecommute candidates.

Applicants must be authorized to work in the U.S.

Additional ways to apply

Preferred Skills

Dominik Sobaszek is recruiting for this position and the positions below.
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CyberCoders, Inc is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.

Your Right to Work – In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification document form upon hire.