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uvm Jobs

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CONTRACT- Senior Verification Engineer
Campbell, CA
Contract $45.00-$60.00
Posted 02/23/2021
If you are a Senior Verification Engineer with experience, please read on! Job Title: Senior Verification Engineer Job Location: Campbell, CA Salary: $45-$55/ hr Duration: 8-12 months Requir...
  • UVM
  • Design Verification
  • C
Senior Design Verification Engineer
Campbell, CA
Full-time $140k - $180k
Posted 12/03/2020
If you are a Senior Design Verification Engineer with experience, please read on! Top Reasons to Work with Us 1. Based in Campbell, we are a semiconductor company. 2. Our company has been around for o...
  • UVM
  • Verification
  • Verilog
  • Python
  • Shell
Senior Design Verification Engineer
Austin, TX
Full-time $140k - $175k
Posted 12/03/2020
If you are a Senior Design Verification Engineer with experience, please read on! Top Reasons to Work with Us 1. Based in Cedar Park area, we are a semiconductor company. 2. Our company has been aroun...
  • UVM
  • Verification
  • Verilog
  • Python
  • Shell
Senior Design Verification Engineer
Campbell, CA
Full-time $150k - $180k
Posted 02/11/2021
If you are a Senior Design Verification Engineer with experience, please read on! Job Title: Senior Design Verification Engineer Job Location: Campbell, CA Salary: $150,000-$180,000 Requiremen...
  • UVM
  • Verification
  • Verilog
  • Python
  • Shell
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Senior Design Verification Engineer
Austin, TX
Full-time $140k - $170k
Posted 02/11/2021
If you are a Senior Design Verification Engineer with experience, please read on! Job Title: Senior Design Verification Engineer Job Location: Austin, TX Salary: $140,000-170,000 Requirements:...
  • UVM
  • Verification
  • Verilog
  • Python
  • Shell
REMOTE- Product Engineering Architect (SoC design)
Campbell, CA
Full-time $150k - $200k
Posted 02/23/2021
If you are a Product Engineering Architect with experience, please read on! Job Title: Product Engineering Architect Job Location: REMOTE Salary: $150,000-$200,000 Requirements: Support simula...
  • UVM
  • Simulation
  • Customer Facing
  • Customer
  • Verification
Director of Design Verification
Campbell, CA
Full-time $200k - $250k
Posted 12/10/2020
If you are a Director of Design Verification with experience, please read on! Top Reasons to Work with Us 1. Based in Campbell, we are a semiconductor company 2. Our company has been around for over a...
  • UVM
  • RTL
  • Verilog
  • SOC
  • ASIC
Verification Engineer
Santa Clara, CA
Full-time $140k - $175k
Posted 02/11/2021
If you are a Verification Engineer with 4+ years experience, please read on! Top Reasons to Work with Us 1. Based in Santa Clara, we are a leading developer of low-power, high-definition and Ultra HD...
  • UVM
  • SystemVerilog
  • Verilog
  • C++
  • Verification
Verification Engineer
Santa Clara, CA
Full-time $150k - $175k
Posted 02/11/2021
If you are a Verification Engineer with 4+ years experience, please read on! Job Title: Verification Engineer Job Location: Santa Clara, CA Salary: $150,000- 175,000 + RSU's Requirements: UVM,...
  • UVM
  • SystemVerilog
  • Verilog
  • C++
  • Verification
Director of Product Engineering
Campbell, CA
Full-time $200k - $250k
Posted 12/12/2020
If you are a Director of Product Engineering with experience, please read on! Top Reasons to Work with Us 1. Based in Campbell, we are a semiconductor company 2. Our company has been around for over a...
  • UVM
  • Product Engineering
  • EDA
  • RTL
  • C++
ASIC Design Verification Engineer
San Diego, CA
Full-time $130k - $170k
Posted 02/25/2021
We are a rapidly growing Cellular SOC leader with a global presence, working on the most cutting-edge 5G & Wifi SOC technology on the market! We have a vibrant, up-beat startup environment where you'...
  • UVM
  • ASIC Verification
  • VHDL
  • Verilog
  • SystemVerilog
Senior ASIC Verification Engineer
San Diego, CA
Full-time $140k - $180k
Posted 01/21/2021
We are a rapidly growing leader with a global presence, working on the most cutting-edge iOT & 5G SOC technology on the market! We have a vibrant, up-beat startup environment where you'll be exposed...
  • UVM
  • ASIC Verification
  • SystemVerilog
  • SOC
  • RF
ASIC Design Engineer
Santa Clara, CA
Full-time $150k - $170k
Posted 02/11/2021
If you are an ASIC Design Engineer with 4+ years experience, please read on! Job Title: ASIC Design Engineer Job Location: Santa Clara, CA Salary: $150,000 - 170,000 + RSU's Requirements: SoC,...
  • UVM
  • ASIC
  • Image Processing
  • Video compression
  • C++
ASIC Design Engineer
Santa Clara, CA
Full-time $150k - $170k
Posted 02/11/2021
If you are a ASIC Design Engineer with 4+ years experience, please read on! Top Reasons to Work with Us 1. Based in Santa Clara, we are a leading developer of low-power, high-definition and Ultra HD v...
  • UVM
  • ASIC
  • Image Processing
  • Video compression
  • C++
REMOTE! RTL Verification Engineer (Mid/Sr) - SoC UVM/Perl/Python
Santa Clara, CA
Compensation Unspecified
Posted 01/12/2021
Located in beautiful Santa Clara, CA we're developing deep neural network computing chips across several industries. We are very well funded and are growing out our team. If you're interested in deep...
  • Implementing SOC UVM coverage-based verification
  • RTL Verification
  • Perl or Python
  • Professional verification engineering
  • C++
ASIC SOC Verification Engineer
Milpitas, CA
Full-time $120k - $190k
Posted 02/25/2021
If you are an ASIC SOC Verification Engineer with experience, please read on! We are an innovative cloud solutions startup located outside of San Francisco backed by incredible investors (funded Zoom...
  • UVM
  • SystemVerilog
  • C
  • Computer Engineering
  • C++
REMOTE! Verification Engineer (Mid/Sr) - RTL/Verilog
Santa Clara, CA
Compensation Unspecified
Posted 01/21/2021
Located in beautiful Santa Clara, CA we're developing deep neural network computing chips across several industries. We are very well funded and are growing out our team. If you're interested in deep...
  • Implementing SOC UVM coverage-based verification
  • RTL Verification
  • Verilog
  • Perl or Python
  • Professional verification engineering
ASIC Verification Engineer
San Jose, CA
Full-time $120k - $150k
Posted 02/19/2021
If you are an ASIC Verification Engineer with experience, please read on! We are an innovative cloud solutions startup located outside of San Francisco backed by incredible investors (funded Zoom, Fi...
  • UVM
  • SystemVerilog
  • C
  • C++
  • System Verilog
 
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